Freedom E310简介
本帖最后由 小飞飞 于 2020-9-29 10:38 编辑Freedom E300平台是由SiFive公司推出的，SiFIve是由美国加州大学伯克利分校发明RISC-V架构的几个主要发起人创办的商业公司，力图加速RISC-V的商业化进程和生态推广。
Freedom E310是使用E300平台配置出来的一个开源SoC，其处理器核心是RISC-V架构的开源处理器E3 Coreplex，架构配置为RV32IMAC，配备16KB指令缓存和16KB SRAM、硬件乘除法器、调试模块等，并包含了丰富的外设，其结构框图如下：
该项目在GitHub上开源，项目地址为：https://github.com/sifive/freedom
项目文件可点此下载：
该项目的说明如下（转自该项目在GitHub上的介绍）：
FreedomThis repository contains the RTL created by SiFive for its Freedom E300 and U500platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300Platform and is designed to be mapped onto an Arty FPGA EvaluationKit. The FreedomU500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed tobe mapped onto a VC707 FPGA EvaluationKit.Both systems boot autonomously and can be controlled via an external debugger.
Please read the section corresponding to the kit you are interested in forinstructions on how to use this repo.
Software RequirementTo compile the bootloaders for both Freedom E300 Arty and U500 VC707FPGA dev kits, the RISC-V software toolchain must be installed locally andset the $(RISCV) environment variable to point to the location of where theRISC-V toolchains are installed. You can build the toolchain from scratchor download the tools here: https://www.sifive.com/products/tools/
Freedom E300 Arty FPGA Dev KitThe Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
How to buildThe Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit isMakefile.e300artydevkit and it consists of two main targets:
[*]verilog: to compile the Chisel source files and generate the Verilog files.
[*]mcs: to create a Configuration Memory File (.mcs) that can be programmedonto an Arty FPGA board.
To execute these targets, you can run the following commands:
$ make -f Makefile.e300artydevkit verilog$ make -f Makefile.e300artydevkit mcs
Note: This flow requires Vivado 2017.1. Old versions are known to fail.
These will place the files under builds/e300artydevkit/obj.
Note that in order to run the mcs target, you need to have the vivadoexecutable on your PATH.
BootromThe default bootrom consists of a program that immediately jumps to address0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Artyboard.
Using the generated MCS ImageFor instructions for getting the generated image onto an FPGA and programming it with software using the Freedom E SDK, please see the Freedom E310 Arty FPGA Dev Kit Getting Started Guide.
Freedom U500 VC707 FPGA Dev KitThe Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
How to buildThe Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit isMakefile.u500vc707devkit and it consists of two main targets:
[*]verilog: to compile the Chisel source files and generate the Verilog files.
[*]mcs: to create a Configuration Memory File (.mcs) that can be programmedonto an VC707 FPGA board.
To execute these targets, you can run the following commands:
$ make -f Makefile.u500vc707devkit verilog$ make -f Makefile.u500vc707devkit mcs
Note: This flow requires Vivado 2016.4. Newer versions are known to fail.
These will place the files under builds/u500vc707devkit/obj.
Note that in order to run the mcs target, you need to have the vivadoexecutable on your PATH.
BootromThe default bootrom consists of a bootloader that loads a program off the SDcard slot on the VC707 board.
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