FreedomThis repository contains the RTL created by SiFive for its Freedom E300 and U500platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300Platform and is designed to be mapped onto an Arty FPGA EvaluationKit. The FreedomU500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed tobe mapped onto a VC707 FPGA EvaluationKit.Both systems boot autonomously and can be controlled via an external debugger.
Please read the section corresponding to the kit you are interested in forinstructions on how to use this repo.
Software RequirementTo compile the bootloaders for both Freedom E300 Arty and U500 VC707FPGA dev kits, the RISC-V software toolchain must be installed locally andset the $(RISCV) environment variable to point to the location of where theRISC-V toolchains are installed. You can build the toolchain from scratchor download the tools here: https://www.sifive.com/products/tools/
Freedom E300 Arty FPGA Dev KitThe Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
How to buildThe Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit isMakefile.e300artydevkit and it consists of two main targets:
verilog: to compile the Chisel source files and generate the Verilog files.
mcs: to create a Configuration Memory File (.mcs) that can be programmedonto an Arty FPGA board.
To execute these targets, you can run the following commands:
$ make -f Makefile.e300artydevkit verilog$ make -f Makefile.e300artydevkit mcs
Note: This flow requires Vivado 2017.1. Old versions are known to fail.
These will place the files under builds/e300artydevkit/obj.
Note that in order to run the mcs target, you need to have the vivadoexecutable on your PATH.
BootromThe default bootrom consists of a program that immediately jumps to address0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Artyboard.