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这是一篇来自“All about circuits”的文章，作者基于其团队在过去5年PUPL项目的探索，分享了在学术环境中如何使用开源硬件尤其是RISC-V的话题，觉得非常有价值，推荐给大家阅读。
Utilizing Open Source Hardware in Academic Environments
In this article, Frank K Gürkaynak of ETH Zurich explores and explains his team's process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment.
Five years ago we started the Parallel Ultra Low Power (PULP) project at ETH Zürich together with the University of Bologna under the leadership of Luca Benini. Our goal was to explore novel computing architectures that are able to get the most out of the energy the system uses over a wide operational range starting from tiny systems used in the internet of things (IoT) all the way up to applications in high-performance computing (HPC). It was clear for us that to build such a system we would need a small but efficient processor core. But where to find such a processor core that we could use?
* 5年前的项目（PULP - 并行超低功耗）目标是选用一款精悍的内核做一种创新的计算架构以支持从IoT应用的微小系统到高性能计算较宽范围，都能比较省电。
Exploring Commercial vs. Open-Source Processors
We first investigated available commercial processors. Since our research activities do not result directly in an income that would allow us to pay for regular commercial licenses, we would need to make use of the academic licensing agreements. In all fairness, most processor IP providers had university programmes with reasonable conditions. The problem was that most of these programmes would not allow you to make changes to the architecture, some would need additional licenses for manufacturing actual chips, and most importantly any collaboration we wanted to establish with new partners both from the industry and academia would require additional agreements to be signed that took quite a long time to set up.
So we started to look at open source processors. While there was plenty of Verilog and VHDL code available for various processor cores under different licenses, like many readers at the moment, we were not very sure how well these cores were designed and verified, whether or not they were actually used in practice.
RISC-V in the PULP Project
As an academic institution, we were able to take more risks with our choices and the freedom that an open source processor gives you, both in terms of making enhancements, and in allowing collaboration with anyone without lengthy negotiations about IP ownership was too tempting to pass up. For the first few years, the PULP project used a 32-bit OpenRISC based processor with great success. We were able to improve the performance of our own implementation of OpenRISC cores (called OR10N) to be competitive with state of the art 32-bit processors and these formed the backbone of our successful multi-core systems geared towards ultra-low-power operation.
Figure 1. The PULP system consists of efficient RISC-V cores, peripherals, interconnect solutions, and accelerators that are combined to create different platforms.
RISC-V as a Solution
At the same time, we saw how RISC-V ISA was gaining in popularity. By far the most important issue in deciding what processor to use in your projects is the availability of a development environment, preferably with widely known and used tools. No matter how clever you can get with developing your architectures, if you can not get developers to port their applications to your system with ease, you will not get the results you want. In my opinion, it is precisely this point that the RISC-V ISA made the most contribution to the open source hardware community.
By maintaining a clear and well thought ISA definition, maintained by the RISC-V foundation (of which ETH Zürich is a founding member), it was possible for a large community to provide ports of compilers and tools to support RISC-V. In the meantime, most of these ports were upstreamed and are available out of the box (for example for GCC since version 7.1 released in April 2017).
This is why, early in 2015, we made the switch to RISC-V as well. We were able to use most of the development for our OR10N core and derive our first core implementing the RISC-V ISA called RI5CY and we have continued to use and improve this core over tens of ASICs we have developed throughout the project. We have also adapted RISC-V cores for different use cases, and added specialized cores for applications that have tight resource constraints (Zero/Micro Riscy), as well as adding a 64-bit core called Ariane that is able to boot Linux operating system.
* 使用处理器最关键的是开发环境，基于这方面的考虑，作者的团队在2015年开始切换到Risc V上，并基于过去在OR10N上的积累做成了第一个基于RISC-V ISA的内核称之为RI5CY，并通过项目中做的十几颗ASICs持续提改进内核。他们同时将RISC-V内核用在不同应用场景，并针对一些资源严重受限的应用增加了专用的内核（Zero/Micro Riscy）以及增加了一个64位的内核称之为Ariane，可以启动Linux操作系统。
Figure 2. Our 9-core IoT processor, Mr. Wolf, on a small demonstration board.
After slightly more than 5 years on the project, the PULP project has resulted in 26 ASICs (seen in Figure 3 below) that were taped out and tested in various technologies from early trials in mature 180nm technologies all the way down to our latest design called Poseidon realized using Globalfoundries 22nm technology. And we are not done yet, we are currently involved in many projects and collaborations that make use of our PULP technology and will allow us to develop it further.
Figure 3. All 26 PULP chips that we have taped out in the last 5 years (not to scale).