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RISC-V汇编指南

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    有人预言,RISC-V或将是继Intel和Arm之后的第三大主流处理器体系。欢迎访问全球首家只专注于RISC-V单片机行业应用的中文网站

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    本帖最后由 新ちゃん 于 2020-8-20 22:52 编辑

    原文出处:https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md


    RISC-V Assembly Programmer’s ManualCopyright and License Information

    The RISC-V Assembly Programmer’s Manual is

    © 2017 Palmer Dabbelt palmer@dabbelt.com
    © 2017 Michael Clark michaeljclark@mac.com
    © 2017 Alex Bradbury asb@lowrisc.org


    It is licensed under the Creative Commons Attribution 4.0 International License (CC-BY 4.0). The full license text is available at https://creativecommons.org/licenses/by/4.0/.


    Command-Line Arguments

    I think it’s probably better to beef up the binutils documentation rather than duplicating it here.


    Registers

    ISA and ABI register names for X, F, and CSRs.


    Addressing

    Addressing formats like %pcrel_lo(). We can just link to the RISC-V PS ABI document to describe what the relocations actually do.



    Instruction Set

    Links to the various RISC-V ISA manuals that are supported.



    Instructions

    Here we can just link to the RISC-V ISA manual.


    Instruction Aliases

    ALIAS line from opcodes/riscv-opc.c


    Pseudo Ops

    Both the RISC-V-specific and GNU .-prefixed options.

    The following table lists assembler directives:


    Directive
    Arguments
    Description
    .align
    integer
    align to power of 2 (alias for .p2align)
    .file
    “filename”
    emit filename FILE LOCAL symbol table
    .globl
    symbol_name
    emit symbol_name to symbol table (scope GLOBAL)
    .local
    symbol_name
    emit symbol_name to symbol table (scope LOCAL)
    .comm
    symbol_name,size,align
    emit common object to .bss section
    .common
    symbol_name,size,align
    emit common object to .bss section
    .ident
    “string”
    accepted for source compatibility
    .section
    [{.text,.data,.rodata,.bss}]
    emit section (if not present, default .text) and make current
    .size
    symbol, symbol
    accepted for source compatibility
    .text

    emit .text section (if not present) and make current
    .data

    emit .data section (if not present) and make current
    .rodata

    emit .rodata section (if not present) and make current
    .bss

    emit .bss section (if not present) and make current
    .string
    “string”
    emit string
    .asciz
    “string”
    emit string (alias for .string)
    .equ
    name, value
    constant definition
    .macro
    name arg1 [, argn]
    begin macro definition \argname to substitute
    .endm

    end macro definition
    .type
    symbol, @function
    accepted for source compatibility
    .option
    {rvc,norvc,pic,nopic,push,pop}
    RISC-V options
    .byte

    8-bit comma separated words
    .2byte
    expression [, expression]*
    16-bit comma separated words (unaligned)
    .4byte
    expression [, expression]*
    32-bit comma separated words (unaligned)
    .8byte
    expression [, expression]*
    64-bit comma separated words (unaligned)
    .half
    expression [, expression]*
    16-bit comma separated words (naturally aligned)
    .word
    expression [, expression]*
    32-bit comma separated words (naturally aligned)
    .dword
    expression [, expression]*
    64-bit comma separated words (naturally aligned)
    .dtprelword
    expression [, expression]*
    32-bit thread local word
    .dtpreldword
    expression [, expression]*
    64-bit thread local word
    .sleb128
    expression
    signed little endian base 128, DWARF
    .uleb128
    expression
    unsigned little endian base 128, DWARF
    .p2align
    p2,[pad_val=0],max
    align to power of 2
    .balign
    b,[pad_val=0]
    byte align
    .zero
    integer
    zero bytes

    The following table lists assembler relocation expansions:


    Assembler Notation
    Description
    Instruction / Macro
    %hi(symbol)
    Absolute (HI20)
    lui
    %lo(symbol)
    Absolute (LO12)
    load, store, add
    %pcrel_hi(symbol)
    PC-relative (HI20)
    auipc
    %pcrel_lo(label)
    PC-relative (LO12)
    load, store, add
    %tprel_hi(symbol)
    TLS LE “Local Exec”
    auipc
    %tprel_lo(label)
    TLS LE “Local Exec”
    load, store, add
    %tprel_add(offset)
    TLS LE “Local Exec”
    add

    Labels
    1. loop:
    2.         j loop
    复制代码

    Numeric labels are used for local references. References to local labels are suffixed with ‘f’ for a forward reference or ‘b’ for a backwards reference.
    1. 1:
    2.         j 1b
    复制代码






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    本帖最后由 新ちゃん 于 2020-8-20 22:57 编辑

    Absolute addressing

    The following example shows how to load an absolute address:

    1. .section .text
    2. .globl _start
    3. _start:
    4.             lui a1,       %hi(msg)       # load msg(hi)
    5.             addi a1, a1,  %lo(msg)       # load msg(lo)
    6.             jalr ra, puts
    7. 2:            j 2b

    8. .section .rodata
    9. msg:
    10.             .string "Hello World\n"
    复制代码

    which generates the following assembler output and relocations as seen by objdump:

    1. 0000000000000000 <_start>:
    2.    0:        000005b7                  lui        a1,0x0
    3.                         0: R_RISCV_HI20        msg
    4.    4:        00858593                  addi        a1,a1,8 # 8 <.L21>
    5.                         4: R_RISCV_LO12_I        msg
    复制代码

    Relative addressing

    The following example shows how to load a PC-relative address:

    1. .section .text
    2. .globl _start
    3. _start:
    4. 1:            auipc a1,     %pcrel_hi(msg) # load msg(hi)
    5.             addi  a1, a1, %pcrel_lo(1b)  # load msg(lo)
    6.             jalr ra, puts
    7. 2:            j 2b

    8. .section .rodata
    9. msg:
    10.             .string "Hello World\n"
    复制代码

    which generates the following assembler output and relocations as seen by objdump:
    1. 0000000000000000 <_start>:
    2.    0:        00000597                  auipc        a1,0x0
    3.                         0: R_RISCV_PCREL_HI20        msg
    4.    4:        00858593                  addi        a1,a1,8 # 8 <.L21>
    5.                         4: R_RISCV_PCREL_LO12_I        .L11
    复制代码

    Load Immediate

    The following example shows the li psuedo instruction which is used to load immediate values:

    1. .section .text
    2. .globl _start
    3. _start:

    4. .equ CONSTANT, 0xcafebabe

    5.         li a0, CONSTANT
    复制代码

    which generates the following assembler output as seen by objdump:
    1. 0000000000000000 <_start>:
    2.    0:        00032537                  lui            a0,0x32
    3.    4:        bfb50513                  addi        a0,a0,-1029
    4.    8:        00e51513                  slli        a0,a0,0xe
    5.    c:        abe50513                  addi        a0,a0,-1346
    复制代码

    Load Address

    The following example shows the la psuedo instruction which is used to load symbol addresses:

    1. .section .text
    2. .globl _start
    3. _start:

    4.         la a0, msg

    5. .section .rodata
    6. msg:
    7.             .string "Hello World\n"
    复制代码

    which generates the following assembler output and relocations as seen by objdump:

    1. 0000000000000000 <_start>:
    2.    0:        00000517                  auipc        a0,0x0
    3.                         0: R_RISCV_PCREL_HI20        msg
    4.    4:        00850513                  addi        a0,a0,8 # 8 <_start+0x8>
    5.                         4: R_RISCV_PCREL_LO12_I        .L11
    复制代码

    Constants

    The following example shows loading a constant using the %hi and %lo assembler functions.

    1. .equ UART_BASE, 0x40003000

    2.         lui a0,      %hi(UART_BASE)
    3.         addi a0, a0, %lo(UART_BASE)
    复制代码

    This example uses the li pseudoinstruction to load a constant and writes a string using polled IO to a UART:

    1. .equ UART_BASE, 0x40003000
    2. .equ REG_RBR, 0
    3. .equ REG_TBR, 0
    4. .equ REG_IIR, 2
    5. .equ IIR_TX_RDY, 2
    6. .equ IIR_RX_RDY, 4

    7. .section .text
    8. .globl _start
    9. _start:
    10. 1:      auipc a0, %pcrel_hi(msg)    # load msg(hi)
    11.         addi a0, a0, %pcrel_lo(1b)  # load msg(lo)
    12. 2:      jal ra, puts
    13. 3:      j 3b

    14. puts:
    15.         li a2, UART_BASE
    16. 1:      lbu a1, (a0)
    17.         beqz a1, 3f
    18. 2:      lbu a3, REG_IIR(a2)
    19.         andi a3, a3, IIR_TX_RDY
    20.         beqz a3, 2b
    21.         sb a1, REG_TBR(a2)
    22.         addi a0, a0, 1
    23.         j 1b
    24. 3:      ret

    25. .section .rodata
    26. msg:
    27.             .string "Hello World\n"
    复制代码

    Floating-point rounding modes

    For floating-point instructions with a rounding mode field, the rounding mode can be specified by adding an additional operand. e.g. fcvt.w.s with round-to-zero can be written as fcvt.w.s a0, fa0, rtz. If unspecified, the default dyn rounding mode will be used.

    Supported rounding modes are as follows (must be specified in lowercase):

    • rne: round to nearest, ties to even
    • rtz: round towards zero
    • rdn: round down
    • rup: round up
    • rmm: round to nearest, ties to max magnitude
    • dyn: dynamic rounding mode (the rounding mode specified in the frm field of the fcsr register is used)
    Control and Status Registers

    The following code sample shows how to enable timer interrupts, set and wait for a timer interrupt to occur:

    1. .equ RTC_BASE,      0x40000000
    2. .equ TIMER_BASE,    0x40004000

    3. # setup machine trap vector
    4. 1:      auipc   t0, %pcrel_hi(mtvec)        # load mtvec(hi)
    5.         addi    t0, t0, %pcrel_lo(1b)       # load mtvec(lo)
    6.         csrrw   zero, mtvec, t0

    7. # set mstatus.MIE=1 (enable M mode interrupt)
    8.         li      t0, 8
    9.         csrrs   zero, mstatus, t0

    10. # set mie.MTIE=1 (enable M mode timer interrupts)
    11.         li      t0, 128
    12.         csrrs   zero, mie, t0

    13. # read from mtime
    14.         li      a0, RTC_BASE
    15.         ld      a1, 0(a0)

    16. # write to mtimecmp
    17.         li      a0, TIMER_BASE
    18.         li      t0, 1000000000
    19.         add     a1, a1, t0
    20.         sd      a1, 0(a0)

    21. # loop
    22. loop:
    23.         wfi
    24.         j loop

    25. # break on interrupt
    26. mtvec:
    27.         csrrc  t0, mcause, zero
    28.         bgez t0, fail       # interrupt causes are less than zero
    29.         slli t0, t0, 1      # shift off high bit
    30.         srli t0, t0, 1
    31.         li t1, 7            # check this is an m_timer interrupt
    32.         bne t0, t1, fail
    33.         j pass

    34. pass:
    35.         la a0, pass_msg
    36.         jal puts
    37.         j shutdown

    38. fail:
    39.         la a0, fail_msg
    40.         jal puts
    41.         j shutdown

    42. .section .rodata

    43. pass_msg:
    44.         .string "PASS\n"

    45. fail_msg:
    46.         .string "FAIL\n"
    复制代码

    本篇完


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